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CXB1451Q
VGA/SVGA/XGA digital data serial transmitter
Features * 1 chip transmitter for serial transmission of 18bit color VGA/SVGA/XGA picture * On chip differential cable driver * TTL/CMOS compatible interface * Support 1 pixel/shiftclock mode & 2 pixel/shiftclock mode * +3.3V single power supply * Low power consumption * 80pin Plastic QFP Package (Body size: 14mm x 14mm) Block Digagram & Pin out
LPFB LPFA VCCA VEES VEEA
80 pin QFP (Plastic)
REFREQ
RED0 (0)
RED0 (1)
RED0 (2)
RED0 (3)
RED0 (4)
RED0 (5)
SDATAN
SDATAP
TESTSB
VCCE
VEEE
IDLE
VCCT
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 TESTDT 61 PANEL1 62 PANEL0 63 CKMODE 64 CNTL3 65 CNTL2 66 CNTL1 67 VEEG 68 VCCG 69 VCCT 70 VEET 71 SFTCLK 72 HSYNC 73 VSYNC 74 VEEG 75 VCCG 76 CNTL0 77 BLU1 (5) 78 BLU1 (4) 79 VCCT 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Encoder Parallel to Serial Converter PLL Cable Driver 40 VCCT 39 GRN0 (0) 38 GRN0 (1) 37 GRN0 (2) 36 GRN0 (3) 35 GRN0 (4) 34 GRN0 (5) 33 VEEG 32 VCCG
VEET
31 VEET 30 VCCT 29 BLU0 (0) 28 BLU0 (1) 27 BLU0 (2) 26 VEEG 25 VCCG 24 BLU0 (3) 23 BLU0 (4) 22 BLU0 (5) 21 VEET
GRN1 (5)
GRN1 (4)
GRN1 (2)
RED1 (4)
RED1 (3)
RED1 (2)
BLU1 (0)
BLU1 (1)
VCCT
VEET
BLU1 (2)
GRN1 (3)
RED1 (5)
GRN1 (0)
Fig. 1. Block Diagram & Pin out
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
GRN1 (1)
RED1 (1)
RED1 (0)
BLU1 (3)
VCCT
VEET
E97913-PS
CXB1451Q
Pin List Power/Ground Pin Name VCCT VEET VCCG VEEG VCCE VEEE VCCA VEEA VEES Pin Number 10, 20, 30, 40, 48, 70, 80 1, 11, 21, 31, 41, 71 25, 32, 69, 76 26, 33, 68, 75 54 51 56 57 58 Descriptions TTL power surpply , should be connected to 3.3V 5% TTL ground, connected to 0V Logical core power surpply, connected to 3.3V 5% Logical core ground, connected to 0V Serial driver power surpply, connected to 3.3V 5% Serial driver ground, connected to 0V Analog power surpply, connected to 3.3V 5% Analog ground, connected to 0V Analog substrate, connected to 0V
Digital Signals Pin Name SFTCLK RED1 (5 to 0) GRN1 (5 to 0) BLU1 (5 to 0) RED0 (5 to 0) GRN0 (5 to 0) BLU0 (5 to 0) HSYNC VSYNC CNTL (3 to 0) PANEL (1, 0) CKMODE IDLE SDATAP/N REFREQ 72 14, 15, 16, 17, 18, 19 6, 7, 8, 9, 12, 13 78, 79, 2, 3, 4, 5 42, 43, 44, 45, 46, 47 34, 35, 36, 37, 38, 39 22, 23, 24, 27, 28, 29 73 74 65, 66, 67, 77 62, 63 64 49 52, 53 50 Pin Number Type TTL in TTL in Descriptions Shift clock, for the data fetch at rising or falling edge Pixel data input in 1 pixcel/sftclk mode 2nd pixel data input in 2 pixel/sftclk mode Ignored in 1 pixcel/sftclk mode 1st pixel data input in 2 pixel/sftclk mode Hsync data Vsync data Control data Panel mode select switch Clock mode select switch Idle mode select switch Serial Output & Refclk request input Refclk request detect flag
TTL in TTL in TTL in TTL in TTL in TTL in TTL in Tx TTL out
Special Pin Name Pin Number Descriptions SFTCLK polarity / TEST function control External loop filter
TESTSB/DT 55, 61 LPFA/B 59, 60
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CXB1451Q
Equivalent I/O circuit
VCCT 6k 6k
VCCG 3k
VCCT
TTL-OUT TTL-IN 300
VEET
VEEG
VEET
(a) TTL input equivalent circuit
(b) TTL output equivalent circuit
VCCA
VCCE
LPFA LPFB SDATAP SDATAN
VEEA
VEEE
(c) LPFA/B equivalent circuit
(d) SDATAP/N equivalent circuit
VCCA
VCCG
VCCT
VCCG
TESTDT
TESTSB
VEEA
VEEG
VEET
VEEG
(e) TESTDT equivalent circuit
(f) TESTSB equivalent circuit
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CXB1451Q
Electrical characteristics Tab. 1. Absolute Maximum Rating Description Power supply voltage TTL DC input voltage TTL output current (High) TTL output current (Low) Serial output pin voltage Ambient temperature Storage temperature Symbol VCC VI_T IOH_T IOL_T Vsdout Ta Tstg Min. -0.3 -0.5 -20 0 -0.5 -55 -65 Typ. Max. 4 5.5 0 20 VCC + 0.5 70 150 Unit V V mA ' mA V C C Under bias Comments
Tab. 2. Recommended Operating Conditions Description Power supply voltage (Include VCCT5) Ambient temperature Symbol VCC Ta Min. 3.135 0 Typ. 3.3 Max. 3.465 70 Unit V C Comments
Tab. 3. DC Characteristics (Under the recommended conditons. See Tab. 2) Description Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Output HIGH voltage (TTL) Output LOW voltage (TTL) Output HIGH current (SDATA) Output LOW current (SDATA) Input HIGH voltage (SDATA) Input LOW voltage (SDATA) Supply current Symbol VIH_T VIL_T IIH_T IIL_T VOH_T VOL_T IOH_SD IOL_SD VIH_SD VIL_SD ICC 165 175 215 225 -0.1 14.7 VCC - 0.6 VCC - 0.7 265 275 0 16 -400 2.3 0.4 +0.1 17.3 Min. 2 -0.5 Typ. Max. 5.5 0.8 20 Unit V V A A V V mA mA V V mA mA VIN = VCC VIN = 0 IOH = -0.2mA IOL = 4mA See Fig. 2 Conditions
Common mode voltage XGA, Outputs open SVGA/VGA, Outputs open
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CXB1451Q
VCCA/G/E/T A 61 VCC 55 VEEA/G/E/T CXB1451Q 53 52 A
Fig. 2. IOH_SD and IOL_SD DC measurement Tab. 4. AC Characteristics (Under the recommended conditons. See Tab. 5) Description Input TTL rise time Input TTL fall time Symbol Tir Tir Min. 0.7 0.7 20.0 10.0 38.0 19.0 60.0 30.0 40 4.0 1.0 400 400 130 10 150 350 0.1 25.0 12.5 40.0 20.0 65.0 32.5 Typ. Max. 4.8 4.8 28.0 14.0 48.0 24.0 68.0 34.0 60 Unit ns ns MHz MHz MHz MHz MHz MHz % ns ns ps ps ns ns ns ns ms Conditions 0.8V to 2.0V 2.0V to 0.8V VGA, 1 pixel/sftclk mode VGA, 2 pixel/sftclk mode SVGA, 1 pixel/sftclk mode SVGA, 2 pixel/sftclk mode XGA, 1 pixel/sftclk mode XGA, 2 pixel/sftclk mode Vth = 1.4V XGA 1 pixel/sftclk mode @65MHz See Fig. 4 20 to 80%, CL = 2pF See Fig. 3
SFTCLK frequency
Fsftclk
SFTCLK duty factor Pixel/Sync/Cntl setup to SFTCLK Pixel/Sync/Cntl hold to SFTCLK SDATA rise time SDATA fall time CLOCK mode assert time CLOCK mode deassert time IDLE mode assert time IDLE mode deassert time PLL lockin time
Dsftclk Tsetup Thold Tor Tof TAclk TDclk TAidle TDidle Tlockin
VCCA/G/E/T
51 52
51 FET probe 100
TTL clock VCC 72
CXB1451Q 53
VEEA/G/E/T
Sampling oscilloscope
Fig. 3. SDATA waveform measurement -5-
CXB1451Q
Timing Chart
1/Fsftclk Dsftclk/Fsftclk VIH_T 2.0V SFTCLK 0.8V VIL_T Tir Tif Tsetup Thold Tir REDxx GRNxx BLUxx H/Vsync CNTLx VIH_T 2.0V 0.8V VIL_T Tif Vth
Setup/hold time is refered from fall edge in TESTSB/DT = GND or OPEN rise edge in TESTSB/DT=V CC
Fig. 4. TTL input timing
Tor 100% SDATAP SDATAN 80% 20% 0% Tof
Fig. 5. Serial output timing
Reference clock SDATAP SDATAN REFRQ signal from CXB1452Q REFREQ TDclk TAclk NRZ data
Fig. 6. Refclk request timing
IDLE
NRZ data SDATAP SDATAN TDidle TAidle
Fig. 7. Idle mode timing -6-
CXB1451Q
Operation mode CXB1451Q supports 3 panel mode and 2 clock mode switched by the PANEL (1, 0) and CKMODE pin according to the Tab. 5 & 6. The supporting clock rate are summarized in Tab. 7. These pins are open High TTL inputs. Tab. 5. Panel Mode select PANEL1 L L H H PANEL0 L H L H Supporting panel size & color VGA (640 x 480) 18bit color SVGA (800 x 600) 18bit color XGA (1024 x 768) 18bit color not supported
Tab. 6. Clock Mode select CKMODE L H Supporting clock mode 2 pixel/ShiftClock (2ppc) 1 pixel/ShiftClock (1ppc)
Tab. 7. Operation Mode Panel Mode VGA Clock Mode 1 pixel/SftClk 2 pixel/SftClk 1 pixel/SftClk 2 pixel/SftClk 1 pixel/SftClk 2 pixel/SftClk Color 18bit 18bit 18bit 18bit 18bit 18bit Shift Clock 25MHz 12.5MHz 40MHz 20MHz 65MHz 32.5MHz Dot Clock 25MHz 25MHz 40MHz 40MHz 65MHz 65MHz Serial rate 600Mbps 600Mbps 960Mbps 960Mbps 1560Mbps 1560Mbps
SVGA
XGA
TESTSB/TESTDT pins select the trigger edge of SFTCLK and test mode according to Tab. 8. Tab. 8. SFTCLK polarity & TEST mode TESTSB GND TESTDT GND OPEN VCC OPEN VCC Fabricator reserved TEST mode
Transmitter operation trigger = falling edge
SDATAP = H SDATAP = L Trigger = rising edge SDATAN = L SDATAN = H
IDLE pin disable differential signal transmission from SDATAP/N pins. It's open High TTL input. Transmission is disabled when IDLE = High.
-7-
CXB1451Q
Applications CXB1451Q GVIF transmitter is applied to the digital RGB signal transmittion for P/C with LCD monitor Video on demand system Monitoring system Graphical controller Projector Digital TV monitor with GVIF receiver, CXB1452Q.
CXB1451Q GVIF Transmitter
RED1 (5 to 0) GRN1 (5 to 0) BLU1 (5 to 0) RED0 (5 to 0) GRN0 (5 to 0) BLU0 (5 to 0) SYNC/CNTL SHIFTCLOCK
6 6 6 6 6 6 6
Encoder
Parallel to Serial Converter
Cable Driver
PLL
STP or Twin axial
Cable Equalizer RED0/GRN0/BLU0 are active in 2pixel/shiftclock mode only PLL
Decoder
Serial to Parallel Converter
6 6 6 6 6 6 6
RED1 (5 to 0) GRN1 (5 to 0) BLU1 (5 to 0) RED0 (5 to 0) GRN0 (5 to 0) BLU0 (5 to 0) SYNC/CNTL SHIFTCLOCK
CXB1452Q GVIF Receiver
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CXB1451Q
Application Cicuit (A) Clock mode: 1 pixel/sftclk (1ppc) Picture sync: H/V sync & DE Color depth: 18bit
VCC Connector 0.1 to 0.4n (3) T 0.1 to 0.4n (3) SW0 Select SFTCLK polarity according to Tab. 8 1k 33 16V 0.1 to 0.4n (3) 51 (1) E E E 51 (1) (1) CHIP RESISTOR (1%) (2) CHIP CAPACITOR (3) FORMED BY THE PRINTED CIRCUIT PATTERN (L = 0.5 to 1.0mm/W = 0.5 to 1.0mm)
Differential cable
0.1 to 0.4n (3) E
330 SW1
1.5k (1) 680p 0.01 1.5k (1) (2) (2)
0.1 0.1 (2) (2)
ON : transmit data OFF : Idle
T
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
0.1 (2)
RED0 (1)
SDATAP
VEES
RED0 (0)
SDATAN
LPFA
REFREQ
Select panel resolution according to Tab. 5 SW2
330
61 TESTDT 62 PANEL1 63 PANEL0
RED0 (2)
RED0 (3)
RED0 (4)
RED0 (5)
LPFB
VCCE
TESTSB
VCCA
VEEA
VEEE
VCCT
VEET
VCCT 40 GRN0 (0) 39 GRN0 (1) 38 GRN0 (2) 37 GRN0 (3) 36 GRN0 (4) 35 GRN0 (5) 34 VEEG 33 VCCG 32 VEET 31 VCCT 30 BLU0 (0) 29 BLU0 (1) 28 BLU0 (2) 27 VEEG 26 VCCG 25 BLU0 (3) 24 BLU0 (4) 23 E 0.1 (2) T E
IDLE
T
SW3
T
330
64 CKMODE 65 CNTL3 66 CNTL2 67 CNTL1 68 VEEG
E T
69 VCCG 70 VCCT 71 VEET 72 SFTCLK 73 HSYNC 74 VSYNC
0.1 (2)
75 VEEG E 76 VCCG 77 CNTL0 78 BLU1 (5)
GRN1 (3)
GRN1 (4)
GRN1 (5)
GRN1 (2)
GRN1 (1)
GRN1 (0)
79 BLU1 (4)
BLU0 (5) 22
T
80 VCCT
RED1 (5)
BLU1 (2)
RED1 (4)
BLU1 (1)
RED1 (3)
BLU1 (0)
RED1 (2)
RED1 (1)
BLU1 (3)
RED1 (0)
VEET 21
VCCT
0.1 (2)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
VCCT
VEET
VEET
0.1 (2)
T T
HSYNC
VSYNC
DE
SFTCLK
5 MSB
4
3
2
1
0 LSB
5 MSB
4
3
2
1
0 LSB
5 MSB
4
3
2
1
0 LSB
BLUE DATA
GREEN DATA
RED DATA
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXB1451Q
Application Cicuit (B) Clock mode: 2 pixel/sftclk Picture sync: ENABLE only Color depth: 12bit
Differential cable VCC Connector 0.1 to 0.4n (3) T 0.1 to 0.4n (3) SW0 Select SFTCLK polarity according to Tab. 8 1k 33 16V 0.1 to 0.4n (3) 51 (1) E E E 51 (1) 330 SW1 0.1 (2) 680p (2) 0.1 (2) (1) CHIP RESISTOR (1%) (2) CHIP CAPACITOR (3) FORMED BY THE PRINTED CIRCUIT PATTERN (L = 0.5 to 1.0mm/W = 0.5 to 1.0mm)
0.1 to 0.4n (3) E
ON : transmit data OFF : Idle
1.5k (1)
T
0.01 1.5k (1) (2)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
0.1 (2) 3210 MSB LSB ODD RED DATA
REFREQ
RED0 (1)
RED0 (2)
RED0 (3)
RED0 (4)
TESTSB
VCCA
VEEA
SDATAP
VEES
VEEE
IDLE
RED0 (0)
SDATAN
LPFA
Select panel resolution according to Tab. 5 SW2
330
61 TESTDT 62 PANEL1 63 PANEL0
RED0 (5)
LPFB
VCCE
VCCT
VEET
VCCT 40 GRN0 (0) 39 GRN0 (1) 38 GRN0 (2) 37 GRN0 (3) 36 GRN0 (4) 35 GRN0 (5) 34 VEEG 33 VCCG 32 VEET 31 VCCT 30 BLU0 (0) 29 BLU0 (1) 28 BLU0 (2) 27 VEEG 26 VCCG 25 BLU0 (3) 24 BLU0 (4) 23 E T E
T
SW3
330
64 CKMODE 65 CNTL3 66 CNTL2 67 CNTL1 68 VEEG
E T
69 VCCG 70 VCCT 71 VEET 72 SFTCLK 73 HSYNC 74 VSYNC
3210 MSB LSB ODD GREEN DATA
0.1 (2)
75 VEEG E 76 VCCG 77 CNTL0 78 BLU1 (5)
0.1 (2)
GRN1 (3)
GRN1 (2)
GRN1 (4)
GRN1 (5)
GRN1 (1)
GRN1 (0)
79 BLU1 (4) T 80 VCCT
BLU0 (5) 22
RED1 (5)
RED1 (4)
RED1 (3)
RED1 (2)
RED1 (1)
BLU1 (3)
RED1 (0)
BLU1 (2)
BLU1 (1)
BLU1 (0)
VEET 21
VCCT
VEET
0.1 (2)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
VEET
VCCT
0.1 (2)
T T 3210 MSB LSB ODD BLUE DATA ODD PIXEL EVEN PIXEL
ENABLE
SFTCLK
3210 MSB LSB EVEN BLUE DATA
3210 MSB LSB EVEN GREEN DATA
3210 MSB LSB EVEN RED DATA
Transmission order of the PIXEL
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 10 -
CXB1451Q
Recommended Printed Circuit Board Structure
L1: Cu plate (18m) + solder coat I1: Adhesive Sheet (0.3mm 0.09mm) L2: Cu plate (36m) I2: Fiber-glass epoxy core (0.8mm) L3: Cu plate (36m) I3: Adhesive Sheet (0.3mm) L4: Cu plate (18m) + solder coat
Recommended Printed Circuit Board Pattern SDATAP/SDATAN pins to the connector path other path POWER and special signal routing example
0.5mm
W = 0.50mm (Z0 = 50) W = 0.25mm
G E E
G Through hole to the GND plane (L2) E T Through hole to the VCCE/VCCG plane (L3) Through hole to the VCCT plane (L3) Chip capacitor Chip resistor
L2 doesn't have plane in this area 41 60
REFREQ
RED0 (1)
RED0 (3)
RED0 (0)
RED0 (2)
RED0 (4)
SDATAN
TESTSB
LPFA
RED0 (5)
SDATAP
G
LPFB
VCCA
VCCE
VCCT
VEES
VEEA
VEEE
61
TESTDT PANEL1 PANEL0 CKMODE CNTL3 CNTL2 CNTL1 VEEG VCCG VCCT VEET SFTCLK HSYNC VSYNC VEEG G T T T T T T T T G VCCG CNTL0 BLU1 (5) BLU1 (4) E E E G
IDLE
VEET
VCCT GRN0 (0) GRN0 (1) GRN0 (2) GRN0 (3) GRN0 (4) GRN0 (5) VEEG VCCG VEET VCCT BLU0 (0) BLU0 (1) BLU0 (2) VEEG VCCG BLU0 (3) BLU0 (4) BLU0 (5) VEET
40
G
G
E
E
80
VCCT
21 G
RED1 (4)
RED1 (2)
GRN1 (5)
GRN1 (3)
GRN1 (1)
RED1 (5)
RED1 (3)
RED1 (1)
RED1 (0)
BLU1 (3)
BLU1 (1)
VCCT
BLU1 (2)
BLU1 (0)
GRN1 (4)
GRN1 (2)
G 1
GRN1 (0)
20 G
- 11 -
VCCT
VEET
VEET
CXB1451Q
1.56Gb/s SDATAP Output waveform
40.1820ns Ch. 1 = 100.0mVolts/div Timebase = 100ps/div
40.6820ns Offset = -92.00mVolts Delay = 40.6820ns
41.1820ns
SFTCLK Jitter tolerance: example power spectrum available for transmission
XGA 2ppc mode 32.5MHz REF LVL 0dBm D
ATTEN 10dB RL 0dBm 10dB/
CENTER 32.50MHz RBW 100kHz
VBW 100kHz
SPAN 10.00MHz SWP 50.0ms
- 12 -
CXB1451Q
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
+ 0.35 1.5 - 0.15 + 0.1 0.127 - 0.05 0.1 41 40
16.0 0.4 + 0.4 14.0 - 0.1 60 61
80 1 0.65 20 0.24
21
+ 0.15 0.1 - 0.1
M 0 to 10
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L03 QFP080-P-1414 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.6g
- 13 -
0.5 0.2
+ 0.15 0.3 - 0.1
(15.0)

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